During fabrication of semiconductor devices such as flash electrically erasable programmable read-only memories (EEPROM), various transistor designs having different properties are formed on a single die of a device. A single die may comprise high voltage complimentary metal oxide semiconductor (CMOS) devices, low voltage CMOS devices, and NAND cells. High voltage devices formed in the device periphery may comprise a thick gate oxide, for example to a thickness of about 20 nanometers (nm) or more, have an active area width of from about 0.5 microns (μ) to about 100μ, and have a gate length of from about 0.5μ to about 10μ with current technology. Low voltage devices formed in the periphery may comprise a gate oxide thickness of from about 5 nm to about 10 nm and have an active area width and a channel length which is about ⅕ the length of the high voltage devices, while NAND cells formed in the array have a tunnel oxide thickness similar to the low voltage devices, an active area length less than about 100 nm and a channel length of less than about 100 nm.
To form the gate oxide and tunnel oxide for the CMOS and NAND devices, a thick gate/tunnel oxide material suitable for high voltage CMOS devices is formed over the high and low CMOS device areas and the NAND device areas of the semiconductor wafer substrate assembly. Next, the high voltage CMOS areas are masked and etched to thin the gate/tunnel oxide over the low voltage CMOS device and NAND device areas. Device manufacture then continues to form floating gates for the NAND devices, and control gates for the NAND devices and the CMOS devices.
Transistor device reliability is a concern with semiconductor processing, particularly as device widths decrease. One reliability problem which occurs more frequently in miniaturized flash memory device transistors is degradation of the tunnel oxide during repeated program and erase cycles.
One method used to improve device reliability, particularly reliability of NAND cells, is nitridation of the tunnel oxide. This may be performed using nitridation or an anneal in an ambient comprising NH3, NO, or NO2 before forming the floating gates and control gates. Nitridation of the tunnel oxide is known to improve tunnel oxide reliability for NAND devices. However, nitridation of the gate oxide of high and low voltage CMOS devices which are also found on the device is not desirable. Nitridation of CMOS device gate oxide is known to degrade the mobility of electrons through the transistor channel region. Since the tunnel oxide of NAND devices found in the array and CMOS devices found in the periphery are formed at the same time, forming a concentration of nitrogen within the tunnel oxide without increasing the concentration within the gate oxide is difficult.
A method for forming CMOS and NAND devices having different nitrogen concentration profiles in the gate/tunnel oxide, and devices resulting from the process, would be desirable.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.